There has been explosive growth in Internet traffic due to the increased number of Internet users, various service demands from those users, the implementation of new services, such as voice-over-IP (VoIP) or streaming applications, and the development of mobile Internet. Conventional routers, which act as relaying nodes connected to sub-networks or other routers, have accomplished their roles well, in situations in which the time required to process packets, determine their destinations, and forward the packets to the destinations is usually smaller than the transmission time on network paths. More recently, however, the packet transmission capabilities of high-bandwidth network paths and the increases in Internet traffic have combined to outpace the processing capacities of conventional routers.
This has led to the development of massively parallel, distributed architecture routers. A distributed architecture router typically comprises a large number of routing nodes that are coupled to each other via a plurality of switch fabric modules and an optional crossbar switch. Each routing node has its own routing (or forwarding) table for forwarding data packets via other routing nodes to a destination address.
The Applicants have filed a number of patent applications related to a massively parallel, distributed architecture router in which each of the multiple routing nodes uses two processors—an inbound network processor and an outbound network processor—to forward data packets. The inbound network processor receives data packets from external devices and forwards the received data packets to other routing nodes via the switch fabric and crossbar switch. The outbound network processor receives data packets from the switch fabric and crossbar switch and forwards the received data packets to an external device.
The disclosed inbound and outbound network processors comprise multiple microengines that perform route searches in a shared forwarding table. In an exemplary embodiment, each inbound or outbound network processor comprises a control plane processor (e.g., XScale core processor (XCP)) operating in the control plane and sixteen (16) microengines that route data packets in the data plane. In such an embodiment, the control plane processors of the inbound and outbound network processors perform control plane communications primarily using Local Processor Communications (LPC) over a PCI bus. Also, mechanisms are available inside each network processor to provide internal communications among microengines and control plane processors inside the same network processor.
The routers previously described by the Applicants distribute the control plane processing and data plane processing across many processors, microengines, processes, and threads. These processing entities must coordinate operations, as well as share variables and hardware resources. Traditional methods of sharing variables and resources include using software semaphores and time-partitioning techniques. However, software semaphores are complex, error-prone, and consume a large amount of system resources. Time-partitioning may not be practical and it is often difficult to maintain synchronization. Additionally, conventional techniques for sharing resources require a specialized programming model that departs from standard Von Neuman programming.
Therefore, there is a need in the art for an improved high-speed router that implements multiprocessor routing nodes that are capable of sharing variables and hardware resources without relying on software semaphores. There is a further need for an improved high-speed router that implements multiprocessor routing nodes that are capable of sharing variables and hardware resources without relying on time partitioning techniques. More particularly, there is need for an improved high-speed router that implements multiprocessor routing nodes without departing from standard Von Neuman processing techniques.